User Tools
en:msx:carnivore2:specification
Differences
This shows you the differences between two versions of the page.
| Next revision | Previous revision | ||
|
en:msx:carnivore2:specification [2020-07-23 20:09] 127.0.0.1 external edit |
en:msx:carnivore2:specification [2024-02-27 08:53] (current) GreyWolf |
||
|---|---|---|---|
| Line 1: | Line 1: | ||
| ====== Technical description of Carnivore2 ====== | ====== Technical description of Carnivore2 ====== | ||
| - | This is the detailed technical description and documentation for the multi-functional [[carnivore2-en|Carnivore2]] cartridge that was created by RBSC. | + | This is the detailed technical description and documentation for the multi-functional [[carnivore2|Carnivore2]] cartridge that was created by RBSC. |
| **NOTE:** The hexadecimal numbers are shown as ''#90'', ''90h'' or ''0x90'' | **NOTE:** The hexadecimal numbers are shown as ''#90'', ''90h'' or ''0x90'' | ||
| Line 13: | Line 13: | ||
| * Utilities compatible with MSX-DOS versions 1 and 2 | * Utilities compatible with MSX-DOS versions 1 and 2 | ||
| * The cartridge can be configured as a RAM extension, IDE disk, FMPAC and SCC/SCC+ sound cards, or a combination of these devices | * The cartridge can be configured as a RAM extension, IDE disk, FMPAC and SCC/SCC+ sound cards, or a combination of these devices | ||
| - | * RAM: 2048 Kb (2 Mb) | + | * RAM: 2048 KB (2 MB) |
| * Includes: | * Includes: | ||
| - | * 1024 Kb main RAM with mapper | + | * 1024 KB main RAM with mapper |
| - | * 256 Kb for ROM shadowing | + | * 256 KB for ROM shadowing |
| - | * 720 Kb additional RAM with a mapper, similar to MegaRAM | + | * 720 KB additional RAM with a mapper, similar to MegaRAM |
| - | * 4 Kb (in the last 64 Kb–block) for the FMPAC SRAM (a backup battery is needed to save data after turning off the power) | + | * 4 KB FMPAC SRAM (a backup battery is needed to save data after turning off the power) |
| - | * Flash memory (FlashROM): 8 Mb capacity, 64 Mb/s | + | * Flash memory (FlashROM): 8 MB capacity, 64 Mbit/s |
| - | * The first 256 Kb are used for service information and ROM BIOSes | + | * The first 256 KB are used for service information and ROM BIOSes |
| * Mapper emulation: | * Mapper emulation: | ||
| - | * Linear 64 Kb mode | + | * Linear 64 KB mode |
| * ASCII8 | * ASCII8 | ||
| * ASCII16 | * ASCII16 | ||
| Line 45: | Line 45: | ||
| |''BOOTCMFC.BIN''| 0 |Boot Menu| | |''BOOTCMFC.BIN''| 0 |Boot Menu| | ||
| |''BIDECMFC.BIN''| 1 |IDE BIOS| | |''BIDECMFC.BIN''| 1 |IDE BIOS| | ||
| - | | | 2 |1Mb RAM| | + | | | 2 |1 MB RAM| |
| |''FMPCCMFC.BIN''| 3 |FMPAC BIOS| | |''FMPCCMFC.BIN''| 3 |FMPAC BIOS| | ||
| Line 53: | Line 53: | ||
| ====== The location of blocks in FlashROM ====== | ====== The location of blocks in FlashROM ====== | ||
| - | The FlashROM chip that is used in Carnivore2 has 8 logical blocks in the first physical 64kb block and then go the rest of 64kb physical blocks. In the logical blocks there are Boot Menu and directory. The next few blocks are allocated for the BIOSes of the embedded devices. | + | The FlashROM chip that is used in Carnivore2 has 8 logical blocks in the first physical 64 KB block and then go the rest of 64 KB physical blocks. In the logical blocks there are Boot Menu and directory. The next few blocks are allocated for the BIOSes of the embedded devices. |
| - | ===== 8kb blocks ===== | + | ===== 8 KB blocks ===== |
| - | The first 8 logical 8kb blocks are grouped into the first physical block that is addressed by | + | The first 8 logical 8 KB blocks are grouped into the first physical block that is addressed by |
| the ''AddrFr'' register. Logical blocks 0, 1, 6 and 7 contain the Boot Menu's code and data. Blocks 2 and 3 contain directory entries. Then go 2 blocks that are reserved for future use. | the ''AddrFr'' register. Logical blocks 0, 1, 6 and 7 contain the Boot Menu's code and data. Blocks 2 and 3 contain directory entries. Then go 2 blocks that are reserved for future use. | ||
| ^ Address range ^ Block number ^ Description ^ | ^ Address range ^ Block number ^ Description ^ | ||
| - | |''000000h–001FFFh''| 0 |after power on (AddrFR=#00, R1Mult="10000101" B1AdrD = #4000) is visible in subslot 0 at address #4000–#5FFF and contains the first 8kb of boot menu (ROM "AB" header + start addresses)| | + | |''000000h–001FFFh''| 0 |after power on (AddrFR=#00, R1Mult="10000101" B1AdrD = #4000) is visible in subslot 0 at address #4000–#5FFF and contains the first 8 KB of boot menu (ROM "AB" header + start addresses)| |
| - | |''002000h–003FFFh''| 1 |after power on is visible in subslot 0 at addresses #6000-#7FFF (bits 2–0 of R1Mult = "101" are the size of the shown block (16kb)) and contain the second 8kb of boot menu| | + | |''002000h–003FFFh''| 1 |after power on is visible in subslot 0 at addresses #6000-#7FFF (bits 2–0 of R1Mult = "101" are the size of the shown block (16 KB)) and contain the second 8 KB of boot menu| |
| |''004000h–005FFFh''| 2 |directory entries| | |''004000h–005FFFh''| 2 |directory entries| | ||
| |''006000h–007FFFh''| 3 |directory entries| | |''006000h–007FFFh''| 3 |directory entries| | ||
| Line 69: | Line 69: | ||
| |''00E000h–00FFFFh''| 7 |used for the data of the Boot Menu| | |''00E000h–00FFFFh''| 7 |used for the data of the Boot Menu| | ||
| - | ===== 64kb blocks ===== | + | ===== 64 KB blocks ===== |
| - | After the first 8 logical 8kb blocks that form the first physical block, there go the physical 64kb blocks of the FlashROM. | + | After the first 8 logical 8 KB blocks that form the first physical block, there go the physical 64 KB blocks of the FlashROM. |
| ^ Address range ^ Physical block number ^ Logical block number ^ Description ^ | ^ Address range ^ Physical block number ^ Logical block number ^ Description ^ | ||
| Line 118: | Line 118: | ||
| The OPLL emulation (FMPAC) that is supported by the cartridge is mapped to ports #7C–7D. | The OPLL emulation (FMPAC) that is supported by the cartridge is mapped to ports #7C–7D. | ||
| - | The FMPAC SRAM is emulated by using the 8kb of the upper area of the 1st megabyte | + | The FMPAC SRAM is emulated by using the 8 KB of the upper area of the 1st megabyte |
| of RAM (shadow RAM) that is not shared with the memory mapper. The physical address | of RAM (shadow RAM) that is not shared with the memory mapper. The physical address | ||
| - | of the 8kb area for SRAM in the shadow RAM is 0FE000h–0FFFFFh. | + | of the 8 KB area for SRAM in the shadow RAM is 0FE000h–0FFFFFh. |
| NOTE: The settings of SRAM will be lost after powering down unless the cartridge | NOTE: The settings of SRAM will be lost after powering down unless the cartridge | ||
| Line 131: | Line 131: | ||
| * 7FF7h: ROM page (read/write) | * 7FF7h: ROM page (read/write) | ||
| - | To enable 8kb of SRAM at address 4000h–5FFFh, set 4Dh to 5FFEh and 69h to 5FFFh. | + | To enable 8 KB of SRAM at address 4000h–5FFFh, set 4Dh to 5FFEh and 69h to 5FFFh. |
| ====== Additional configuration EEPROM ====== | ====== Additional configuration EEPROM ====== | ||
| - | Model: M93C46MN1 (128 bytes/1 kbit)\\ | + | Model: M93C46MN1 (128 bytes/1 Kbit)\\ |
| [[http://www.atmel.com/Images/doc5140.pdf|Datasheet]] | [[http://www.atmel.com/Images/doc5140.pdf|Datasheet]] | ||
| Line 172: | Line 172: | ||
| | 1C | Autostart entry number | | | 1C | Autostart entry number | | ||
| | 1D | Help scroller status | | | 1D | Help scroller status | | ||
| + | | 1E | Dual-PSG status | | ||
| + | | 1F | Autostart delay | | ||
| + | | 20 | Slot 3 usage flag | | ||
| + | | 21 | User-configurable ID and control port number | | ||
| + | |||
| Writing to EEPROM is done via the configuration register ''CardMDR+#23''. The commands for EEPROM are saved into this register in a sequence that is described in the chip's datasheet. Only write–enable, read and write commands are used. | Writing to EEPROM is done via the configuration register ''CardMDR+#23''. The commands for EEPROM are saved into this register in a sequence that is described in the chip's datasheet. Only write–enable, read and write commands are used. | ||
| Line 177: | Line 182: | ||
| ====== Configuration registers ====== | ====== Configuration registers ====== | ||
| - | The configuration registers are located at addresses #0F80 or #4F80 or #8F80 or #CF80h. Their visibility and location is controlled by the main control register's first byte — at address #4F80. The main control register is called ''CardMDR''. After power on, the registers are located at address #4F80. All registers are write–only except the pseudo–register for sending/receiving the data when accessing the FlashROM and the register for the configuration EEPROM. | + | The configuration registers are located at addresses #0F80 or #4F80 or #8F80 or #CF80h. Their visibility and location is controlled by the main control register's first byte — at address #4F80. The main control register is called ''CardMDR''. After power on, the registers are located at address #4F80. All registers are write–only except the pseudo–register for sending/receiving the data when accessing the FlashROM and the register for the configuration EEPROM, as well as 3 bytes of the firmware version - FPGA_ver. |
| Below you can find the description of configuration registers. | Below you can find the description of configuration registers. | ||
| - | ^ Register number, name ^ Bit number ^ Value ^ Description ^ | + | ^ Register number, name ^ Bit number ^ Value ^ Description ^ |
| - | |00 [[#CardMDR]]|Main cartridge's configuration register||| | + | | 00 [[#CardMDR]] | Main cartridge's configuration register ||| |
| - | |01 AddrM0|lower address register (bits 7–0) for accessing the FlashROM||| | + | | 01 AddrM0 | lower address register (bits 7–0) for accessing the FlashROM ||| |
| - | |02 AddrM1|middle address register (bits 15–8) for accessing the FlashROM||| | + | | 02 AddrM1 | middle address register (bits 15–8) for accessing the FlashROM ||| |
| - | |03 AddrM2|higher address register (bits 22–16) for accessing the FlashROM||| | + | | 03 AddrM2 | higher address register (bits 22–16) for accessing the FlashROM ||| |
| - | |04 DatM0|pseudo–register for sending/receiving data from/to FlashROM||| | + | | 04 DatM0 | pseudo–register for sending/receiving data from/to FlashROM ||| |
| - | |05 AddrFR|register controlling the number of FlashROM's 64kb block for ROM emulation \\ The default value of this register is 00h||| | + | | 05 AddrFR | register controlling the number of FlashROM's 64 KB block for ROM emulation \\ The default value of this register is 00h ||| |
| - | |06 R1Mask|[[#bank_config_registers|Configuration registers for bank]] 1||| | + | | 06 R1Mask | [[#bank_config_registers|Configuration registers for bank]] 1 ||| |
| - | |07 R1Addr|:::||| | + | | 07 R1Addr | ::: | ::: | ::: | |
| - | |08 R1Reg|:::||| | + | | 08 R1Reg | ::: | ::: | ::: | |
| - | |09 R1Mult|:::||| | + | | 09 R1Mult | ::: | ::: | ::: | |
| - | |0A B1MaskR|:::||| | + | | 0A B1MaskR | ::: | ::: | ::: | |
| - | |0C R2Mask|[[#bank_config_registers|Configuration registers for bank]] 2||| | + | | 0C R2Mask | [[#bank_config_registers|Configuration registers for bank]] 2 ||| |
| - | |0D R2Addr|:::||| | + | | 0D R2Addr | ::: | ::: | ::: | |
| - | |0E R2Reg|:::||| | + | | 0E R2Reg | ::: | ::: | ::: | |
| - | |0F R2Mult|:::||| | + | | 0F R2Mult | ::: | ::: | ::: | |
| - | |10 B2MaskR|:::||| | + | | 10 B2MaskR | ::: | ::: | ::: | |
| - | |11 B2AdrD|:::||| | + | | 11 B2AdrD | ::: | ::: | ::: | |
| - | |12 R3Mask|[[#bank_config_registers|Configuration registers for bank]] 3||| | + | | 12 R3Mask | [[#bank_config_registers|Configuration registers for bank]] 3 ||| |
| - | |13 R3Addr|:::||| | + | | 13 R3Addr | ::: | ::: | ::: | |
| - | |14 R3Reg|:::||| | + | | 14 R3Reg | ::: | ::: | ::: | |
| - | |15 R3Mult|:::||| | + | | 15 R3Mult | ::: | ::: | ::: | |
| - | |16 B3MaskR|:::||| | + | | 16 B3MaskR | ::: | ::: | ::: | |
| - | |17 B3AdrD|:::||| | + | | 17 B3AdrD | ::: | ::: | ::: | |
| - | |18 R4Mask|[[#bank_config_registers|Configuration registers for bank]] 4||| | + | | 18 R4Mask | [[#bank_config_registers|Configuration registers for bank]] 4 ||| |
| - | |19 R4Addr|:::||| | + | | 19 R4Addr | ::: | ::: | ::: | |
| - | |1A R4Reg|:::||| | + | | 1A R4Reg | ::: | ::: | ::: | |
| - | |1B R4Mult|:::||| | + | | 1B R4Mult | ::: | ::: | ::: | |
| - | |1C B4MaskR|similar to B1MaskR||| | + | | 1C B4MaskR | similar to B1MaskR ||| |
| - | |1D B4AdrD|similar to B1AdrD||| | + | | 1D B4AdrD | similar to B1AdrD ||| |
| - | |1E [[#Mconf]]|Expanded slot configuration register||| | + | | 1E [[#Mconf]] | Expanded slot configuration register ||| |
| - | |1F CMDRCpy|copy of the CardMDR+#00 register (to be used with LDIR command)||| | + | | 1F CMDRCpy | copy of the CardMDR+#00 register (to be used with LDIR command) ||| |
| - | |20 ConfFl|FlashROM chip's configuration \\ The default value of this register is — 010b||| | + | | 20 ConfFl | FlashROM chip's configuration \\ The default value of this register is — 010b ||| |
| - | | | 2 | 0 |8 bit bus| | + | | | 2 | 0 | 8 bit bus | |
| - | |:::|:::| 1 |16 bit bus| | + | | ::: | ::: | 1 | 16 bit bus | |
| - | |:::| 1 |Reset/protect flag|| | + | | ::: | 1 | Reset/protect flag || |
| - | |:::| 0 | 1 |enable 12V for boosted writing into FlashROM| | + | | ::: | 0 | 1 | enable 12V for boosted writing into FlashROM | |
| - | |:::|:::| 0 |зdisable 12V for boosted writing into FlashROM| | + | | ::: | ::: | 0 | зdisable 12V for boosted writing into FlashROM | |
| - | |21 NSReg|Non-standard Register \\ The default value of this register is #00, please don't change it!||| | + | | 21 NSReg | Non-standard Register \\ The default value of this register is #00, please don't change it! ||| |
| - | |22 SndLVL|volume level register \\ The default value of this register is 1Bh (00011011b)||| | + | | 22 SndLVL | volume level register \\ The default value of this register is 1Bh (00011011b) ||| |
| - | | | 7, 6 |10 = FMPAC mono, \\ 00 = FMPAC stereo|| | + | | | 7, 6 | 10 = FMPAC mono, \\ 00 = FMPAC stereo || |
| - | |:::| 5, 4, 3 |FMPAC audio level (0–7)|| | + | | ::: | 5, 4, 3 | FMPAC audio level (0–7) || |
| - | |:::| 2, 1, 0 |SCC/SCC+ audio level (0–7)|| | + | | ::: | 2, 1, 0 | SCC/SCC+ audio level (0–7) || |
| - | |23 CfgEEPR|register for controlling additional configuration EEPROM (93C46)||| | + | | 23 CfgEEPR | register for controlling additional configuration EEPROM (93C46) ||| |
| - | | | 7, 6, 5, 4 |not used|| | + | | | 7, 6, 5, 4 | not used || |
| - | |:::| 3 |EECS signal Chip Select EEPROM|| | + | | ::: | 3 | EECS signal Chip Select EEPROM || |
| - | |:::| 2 |EECK signal CLK (sync)|| | + | | ::: | 2 | EECK signal CLK (sync) || |
| - | |:::| 1 |EEDI signal Data Input (data sent to EEPROM)|| | + | | ::: | 1 | EEDI signal Data Input (data sent to EEPROM) || |
| - | |:::| 0 |EEDO signal Data Output (data received from EEPROM); read–only|| | + | | ::: | 0 | EEDO signal Data Output (data received from EEPROM); read–only || |
| - | |24 PSGCtrl|PSG control register \\ The default value of this register is 1Bh (00011011b)||| | + | | 24 PSGCtrl | PSG control register \\ The default value of this register is 1Bh (00011011b) ||| |
| - | | | 7 |enable/disable PSG|| | + | | | 7 | enable/disable PSG || |
| - | |:::| 6 |enable/disable PPI Clicker|| | + | | ::: | 6 | enable/disable PPI Clicker || |
| - | |:::| 5, 4, 3 |PSG audio level (0–7)|| | + | | ::: | 5, 4, 3 | PSG audio level (0–7) || |
| - | |:::| 2, 1, 0 |PPI Clicker audio level (0–7)|| | + | | ::: | 2, 1, 0 | PPI Clicker audio level (0–7) || |
| - | |25 V_AR_L|lower 8 bits of the interceptor code||| | + | | 25 | reserved for future use ||| |
| - | |26 V_AR_H|сhigher 8 bits of the interceptor code||| | + | | 26 | reserved for future use ||| |
| - | |27 aV_hunt|interceptor's flag for delayed configuration||| | + | | 27 | reserved for future use ||| |
| - | | | 0 |activation flag for interceptor code on system restart or read from #4000|| | + | | | 0 | activation flag for interceptor code on system restart or read from #4000 || |
| - | |:::|:::| 1 |enabled| | + | | ::: | ::: | 1 | enabled | |
| - | |:::| 1 |interceptor code's location|| | + | | ::: | 1 | interceptor code's location || |
| - | |:::|:::| 0 |boot menu in FlashROM| | + | | ::: | ::: | 0 | boot menu in FlashROM | |
| - | |:::|:::| 1 |first shadow RAM block| | + | | ::: | ::: | 1 | first shadow RAM block | |
| - | |28 SLM_cfg|per–device subslot assignment (master slot)||| | + | | 28 SLM_cfg | per–device subslot assignment (master slot) ||| |
| - | | | 7 |FMPAC subslot number|| | + | | | 7 | FMPAC subslot number || |
| - | |:::| 6 |:::|| | + | | ::: | 6 | ::: | ::: | |
| - | |:::| 5 |RAM (Mapper MMM) subslot number|| | + | | ::: | 5 | RAM (Mapper MMM) subslot number || |
| - | |:::| 4 |:::|| | + | | ::: | 4 | ::: | ::: | |
| - | |:::| 3 |IDE (CF) subslot number|| | + | | ::: | 3 | IDE (CF) subslot number || |
| - | |:::| 2 |:::|| | + | | ::: | 2 | ::: | ::: | |
| - | |:::| 1 |FlashROM/SCC subslot number|| | + | | ::: | 1 | FlashROM/SCC subslot number || |
| - | |:::| 0 |:::|| | + | | ::: | 0 | ::: | ::: | |
| - | |29 SCART_cfg|slave slot control register||| | + | | 29 SCART_cfg | slave slot control register ||| |
| - | | | 7 | 1 |slave slot enabled| | + | | | 7 | 1 | slave slot enabled | |
| - | |:::|:::| 0 |slave slot disabled| | + | | ::: | ::: | 0 | slave slot disabled | |
| - | |:::| 6 | 1 |slave slot's location assigned by user| | + | | ::: | 6 | 1 | slave slot's location assigned by user | |
| - | |:::|:::| 0 |slave slot assigned as subslot of master slot| | + | | ::: | ::: | 0 | slave slot assigned as subslot of master slot | |
| - | |:::| 5 | 1 |slave slot expanded (if not used as a subslot of master slot)| | + | | ::: | 5 | 1 | slave slot expanded (if not used as a subslot of master slot) | |
| - | |:::|:::| 0 |slave slot non–expanded (if not used as a subslot of master slot)| | + | | ::: | ::: | 0 | slave slot non–expanded (if not used as a subslot of master slot) | |
| - | |:::| 4 | 1 |master slot's location is assigned by user| | + | | ::: | 4 | 1 | master slot's location is assigned by user | |
| - | |:::|:::| 0 |master slot located at the physical slot| | + | | ::: | ::: | 0 | master slot located at the physical slot | |
| - | |:::| 3 | 1 |not used| | + | | ::: | 3 | 1 | not used | |
| - | |:::|:::| 0 |:::| | + | | ::: | ::: | 0 | ::: | |
| - | |:::| 2 | 1 |allow slot select register for emulated slot (used only for slots 1 and 2)| | + | | ::: | 2 | 1 | allow slot select register for emulated slot (used only for slots 1 and 2) | |
| - | |:::|:::| 0 |disable slot select register for emulated slot (real slot's register will be used)| | + | | ::: | ::: | 0 | disable slot select register for emulated slot (real slot's register will be used) | |
| - | |2A SCART_SLT|slot/subslot configuration on power–on||| | + | | 2A SCART_SLT | slot/subslot configuration on power–on ||| |
| - | | | 7, 6 |00 = mini ROM up to 32kb without mapper \\ 01 = K4 mapper \\ 10 = K5 mapper without SCC \\ 11 = K5 mapper + SCC|| | + | | | 7, 6 | 00 = mini ROM up to 32 KB without mapper \\ 01 = K4 mapper \\ 10 = K5 mapper without SCC \\ 11 = K5 mapper + SCC || |
| - | |:::| 5, 4 |master slot number|| | + | | ::: | 5, 4 | master slot number || |
| - | |:::| 3, 2 |expanded slave slot number|| | + | | ::: | 3, 2 | expanded slave slot number || |
| - | |:::| 1, 0 |slave slot number|| | + | | ::: | 1, 0 | slave slot number || |
| - | |2B SCART_StBl|slave slot's 64kb block assignment in FlashROM||| | + | | 2B SCART_StBl | slave slot's 64 KB block assignment in FlashROM ||| |
| - | |2C, 2D, 2E FPGA_ver|FPGA firmware version (3 ASCII bytes)||| | + | | 2C, 2D, 2E FPGA_ver | FPGA firmware version (3 ASCII bytes) ||| |
| - | |2F|MROM_offs = mini ROM offset in 64kb block (in 8kb steps)||| | + | | 2F | MROM_offs = mini ROM offset in 64 KB block (in 8 KB steps) ||| |
| + | | 30 PSGAlt | PSG port configuration ||| | ||
| + | | | 1 | reserved | | | ||
| + | | ::: | 0 | 1 | alternative ports: #10-#11 | | ||
| + | | ::: | ::: | 0 | default ports: #A0-#A1 | | ||
| + | | 35 PFXN | User-configurable I/O port number for ID and control ||| | ||
| {{anchor:bank_config_registers}} | {{anchor:bank_config_registers}} | ||
| Line 321: | Line 330: | ||
| | 3 | 0 |bank is enabled| | | 3 | 0 |bank is enabled| | ||
| |:::| 1 |bank is disabled| | |:::| 1 |bank is disabled| | ||
| - | | 2, \\ 1, \\ 0 |bank's size \\ 111b = 64 kb, \\ 110b = 32 kb, \\ 101b = 16 kb, \\ 100b = 8 kb, \\ 011b = 4 kb \\ other value — bank is disabled \\ The default value of this register is 85h|| | + | | 2, \\ 1, \\ 0 |bank's size \\ 111b = 64 KB, \\ 110b = 32 KB, \\ 101b = 16 KB, \\ 100b = 8 KB, \\ 011b = 4 KB \\ other value — bank is disabled \\ The default value of this register is 85h|| |
| The default value is 00h (bank is disabled) | The default value is 00h (bank is disabled) | ||
| Line 327: | Line 336: | ||
| ==== BnMaskR ==== | ==== BnMaskR ==== | ||
| - | Bitmask for bank's addressing mode into the FlashROM. This is the ROM's emulated size and the number of pages. For example for a 128kb ROM we will need 16 pages of 8kb, so we set the 0Fh (00001111b) mask. | + | Bitmask for bank's addressing mode into the FlashROM. This is the ROM's emulated size and the number of pages. For example for a 128 KB ROM we will need 16 pages of 8 KB, so we set the 0Fh (00001111b) mask. |
| The default value of this register is 03h | The default value of this register is 03h | ||
| Line 369: | Line 378: | ||
| | 4 | 1 |control 3С порта (МММ mapper)| | | 4 | 1 |control 3С порта (МММ mapper)| | ||
| | 3 | 1 |control -3 Subslot FM Pack bios ROM| | | 3 | 1 |control -3 Subslot FM Pack bios ROM| | ||
| - | | 2 | 1 |control -2 Subslot MMM mapper with 1mb of RAM is enabled| | + | | 2 | 1 |control -2 Subslot MMM mapper with 1 MB of RAM is enabled| |
| | 1 | 1 |control -1 Subslot CF card interface| | | 1 | 1 |control -1 Subslot CF card interface| | ||
| | 0 | 1 |control -0 Subslot MSCC (and this register)| | | 0 | 1 |control -0 Subslot MSCC (and this register)| | ||
| Line 377: | Line 386: | ||
| ====== Directory entry format ====== | ====== Directory entry format ====== | ||
| - | There are 253 user–controlled directory entries available in the cartridge. The first directory entry can't be edited or deleted because it sets the default cartridge's configuration — all enabled. The directory is 8kb in size and is located in the 2 and 3 logical blocks of the FlashROM chip at addresses 004000h–005FFFh (block 2) and 006000h–007FFFh (block 3). The physical block number (controlled by the ''AddrFr'' register) is zero. | + | There are 253 user–controlled directory entries available in the cartridge. The first directory entry can't be edited or deleted because it sets the default cartridge's configuration — all enabled. The directory is 8 KB in size and is located in the 2 and 3 logical blocks of the FlashROM chip at addresses 004000h–005FFFh (block 2) and 006000h–007FFFh (block 3). The physical block number (controlled by the ''AddrFr'' register) is zero. |
| Each directory entry occupies 40h (64 bytes) and has the following format: | Each directory entry occupies 40h (64 bytes) and has the following format: | ||
| Line 383: | Line 392: | ||
| |#00|NUM|Record number (last one — #FF is ignored)|| | |#00|NUM|Record number (last one — #FF is ignored)|| | ||
| |#01|ACT|Active/empty record's flag (#FF — active record)|| | |#01|ACT|Active/empty record's flag (#FF — active record)|| | ||
| - | |#02|STB|Starting 64kb block for data|| | + | |#02|STB|Starting 64 KB block for data|| |
| - | |#03|LNB|Data size in 64kb blocks|| | + | |#03|LNB|Data size in 64 KB blocks|| |
| |#04|MAP|Mapper type symbol|| | |#04|MAP|Mapper type symbol|| | ||
| |#05|NAM|Record name (30 bytes)|| | |#05|NAM|Record name (30 bytes)|| | ||
| Line 414: | Line 423: | ||
| |#3B|[[#Mconf]]|expanded slot configuration register|| | |#3B|[[#Mconf]]|expanded slot configuration register|| | ||
| |#3C|[[#CardMDR]]|main configuration register|| | |#3C|[[#CardMDR]]|main configuration register|| | ||
| - | |#3D|[[#PosSiz]]|size and position in 64kb block for mini ROMs|| | + | |#3D|[[#PosSiz]]|size and position in 64 KB block for mini ROMs|| |
| |#3E|[[#RstRun]]|reset and start options|| | |#3E|[[#RstRun]]|reset and start options|| | ||
| |#3F|Resrv|Reserved|| | |#3F|Resrv|Reserved|| | ||
| Line 420: | Line 429: | ||
| ===== PosSiz ===== | ===== PosSiz ===== | ||
| - | PosSiz — size and position in 64kb block for mini ROMs | + | PosSiz — size and position in 64 KB block for mini ROMs |
| ^ Bit number ^ Value/description ^ | ^ Bit number ^ Value/description ^ | ||
| | 7 |reserved| | | 7 |reserved| | ||
| - | | 6, \\ 5, \\ 4 |offset of mini ROM in 64kb block based on ROM's size: <WRAP> | + | | 6, \\ 5, \\ 4 |offset of mini ROM in 64 KB block based on ROM's size: <WRAP> |
| - | | ^ 8 kb ^ 16 kb ^ 32 kb ^ | + | | ^ 8 KB ^ 16 KB ^ 32 KB ^ |
| - | |000b| 0 kb| 0 kb | 0 kb | | + | |000b| 0 KB | 0 KB | 0 KB | |
| - | |001b| 8 kb| 16 kb | 32 kb | | + | |001b| 8 KB | 16 KB | 32 KB | |
| - | |010b| 16 kb | 32 kb | | | + | |010b| 16 KB | 32 KB | | |
| - | |011b| 24 kb | 48 kb | | | + | |011b| 24 KB | 48 KB | | |
| - | |100b| 32 kb | | | | + | |100b| 32 KB | | | |
| - | |101b| 40 kb | | | | + | |101b| 40 KB | | | |
| - | |110b| 48 kb | | | + | |110b| 48 KB | | |
| - | |111b| 56 kb | | | + | |111b| 56 KB | | |
| </WRAP>| | </WRAP>| | ||
| - | | 3 |non–standard ROM size:\\ 1 — 49 kb \\ 0 — standard ROM size| | + | | 3 |non–standard ROM size:\\ 1 — 49 KB \\ 0 — standard ROM size| |
| - | | 2,\\ 1, \\ 0 |mini ROM's size: \\ 110b = 32 kb \\ 101b = 16 kb \\ 100b = 8 kb \\ 011b = 4 kb \\ 000b = not mini ROM| | + | | 2,\\ 1, \\ 0 |mini ROM's size: \\ 110b = 32 KB \\ 101b = 16 KB \\ 100b = 8 KB \\ 011b = 4 KB \\ 000b = not mini ROM| |
| ===== RstRun ===== | ===== RstRun ===== | ||
| Line 450: | Line 459: | ||
| ====== Mappers ====== | ====== Mappers ====== | ||
| - | The cartridge supports a few common mappers and the linear mode that allows first 64kb of the MiniROM to be visible in the address space. The physical addresses allocated for the mappers' operation lie in the range of 100000h–1FFFFFh. This means that only the second megabyte of RAM is used. | + | The cartridge supports a few common mappers and the linear mode that allows first 64 KB of the MiniROM to be visible in the address space. The physical addresses allocated for the mappers' operation lie in the range of 100000h–1FFFFFh. This means that only the second megabyte of RAM is used. |
| {{anchor:mapper_type}} | {{anchor:mapper_type}} | ||
| Line 458: | Line 467: | ||
| |''a''|[[#ASCII8]] mapper| | |''a''|[[#ASCII8]] mapper| | ||
| |''A''|[[#ASCII16]] mapper| | |''A''|[[#ASCII16]] mapper| | ||
| - | |''M''|[[#minirom|mini ROM (8, 16, 32, 48 and 64kb ROM without mapper)]]| | + | |''M''|[[#minirom|mini ROM (8, 16, 32, 48 and 64 KB ROM without mapper)]]| |
| |''C''|configuration entry| | |''C''|configuration entry| | ||
| |''U''|unknown mapper| | |''U''|unknown mapper| | ||
| Line 468: | Line 477: | ||
| Default configuration values: | Default configuration values: | ||
| |#F8|#60|#00|#84|#FF|#40^bank 1| | |#F8|#60|#00|#84|#FF|#40^bank 1| | ||
| - | |#F8|#68|#01|#84|#FF|#60^bank 2| | + | |#F8|#68|#00|#84|#FF|#60^bank 2| |
| - | |#F8|#70|#02|#84|#FF|#80^bank 3| | + | |#F8|#70|#00|#84|#FF|#80^bank 3| |
| - | |#F8|#78|#03|#84|#FF|#A0^bank 4| | + | |#F8|#78|#00|#84|#FF|#A0^bank 4| |
| |#FF|#AC|#00|#02|#FF| ^configuration registers| | |#FF|#AC|#00|#02|#FF| ^configuration registers| | ||
| Line 479: | Line 488: | ||
| Default configuration values: | Default configuration values: | ||
| |#F8|#60|#00|#85|#FF|#40^bank 1| | |#F8|#60|#00|#85|#FF|#40^bank 1| | ||
| - | |#F8|#70|#01|#85|#FF|#80^bank 2| | + | |#F8|#70|#00|#85|#FF|#80^bank 2| |
| - | |#F8|#70|#02|#08|#3F|#80^bank 3| | + | |#F8|#60|#00|#85|#FF|#С0^bank 3| |
| - | |#F8|#78|#03|#08|#3F|#A0^bank 4| | + | |#F8|#70|#00|#85|#FF|#00^bank 4| |
| |#FF|#8C|#00|#01|#FF| ^configuration registers| | |#FF|#8C|#00|#01|#FF| ^configuration registers| | ||
| Line 510: | Line 519: | ||
| ===== MiniROM ===== | ===== MiniROM ===== | ||
| - | The cartridge supports MiniROM (ROM images up to 49kb) without mapper. | + | The cartridge supports MiniROM (ROM images up to 49 KB) without mapper. |
| Default configuration values: | Default configuration values: | ||
| Line 520: | Line 529: | ||
| {{anchor:linear64}} | {{anchor:linear64}} | ||
| - | ===== Linear 64kb mode ===== | + | ===== Linear 64 KB mode ===== |
| - | The cartridge supports the linear 64kb mode, when the first 64kb of the ROM are visible in the address space. | + | The cartridge supports the linear 64 KB mode, when the first 64 KB of the ROM are visible in the address space. |
| The default configuration values for MiniROMs are: | The default configuration values for MiniROMs are: | ||
| Line 587: | Line 596: | ||
| |#1C|[[#RstRun]]|| | |#1C|[[#RstRun]]|| | ||
| |#1D|Not used, always FF|| | |#1D|Not used, always FF|| | ||
| + | |||
| + | ====== User-defined ID and control port I/O ====== | ||
| + | |||
| + | Carnivore2 can be detected and controlled via its own configurable port #F0-F2. The following I/O operations are possible: | ||
| + | |||
| + | - Detection of the cartridge | ||
| + | * Write "C" to port, then read the value. Carnivore2 will respond with its version - "2" (ASCII format) | ||
| + | - Identify the slot used by Carnivore2 | ||
| + | * Write "S" to port, then read the value. Carnivore2 will respond with its slot, for example "1" (ASCII format) | ||
| + | - Hide control registers | ||
| + | * Write "H" to port, the control registers will be hidden | ||
| + | - Show control registers | ||
| + | * Write "R" to port, control the registers will appear at their defined location (see below) | ||
| + | - Set location for control registers | ||
| + | * Write "0" to port, the control registers will appear at #0F80 | ||
| + | * Write "1" to port, the control registers will appear at #4F80 | ||
| + | * Write "2" to port, the control registers will appear at #8F80 | ||
| + | * Write "3" to port, the control registers will appear at #CF80 | ||
| + | - Set cartridge's device configuration (software reset is required!) | ||
| + | * Write "A" to port, the cartridge will enable only the main slot (one device only) | ||
| + | * Write "M" to port, the cartridge will set the default configuration (all devices enabled) | ||
| ====== Links ====== | ====== Links ====== | ||
| - | [[carnivore2-en]] | + | [[carnivore2]] |
| - | {{tag>MSX RBSC_en}} | + | {{tag>MSX-en RBSC-en}} |
en/msx/carnivore2/specification.1595524144.txt.gz · Last modified: 2020-07-23 20:09 by 127.0.0.1
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Noncommercial-Share Alike 4.0 International
